1. Field of the Invention
The present invention relates to a synchronous memory system having a mode in which address and data signals can be multiplexed on the same set of signal lines.
2. Related Art
In some applications, such as cellular phones, there is a limited space for a printed circuit board (PCB). If an application uses a static random access memory (SRAM) chip that requires a 16-bit data bus and a 14-bit address bus, the associated PCB will require at least 30 corresponding routing wires to enable the SRAM chip to communicate with other chips.
It would therefore be desirable to share the address bus with the data bus, thereby minimizing the number of routing wires required on the PCB. An operating mode in which address and data signals are multiplexed onto the same set of bus lines is hereinafter referred to as a address/data (A/D) muxed mode.
Intel® provides a flash memory that shares an address bus with a data bus. This flash memory is described in more detail in the Datasheet for the Intel® StrataFlash® Cellular Memory (M18) (Order Number 309823). However, this Intel® flash memory can only perform asynchronous write operations, which require the use of extra control signals (i.e., extra PCB routing wires). Moreover, while the Intel® flash memory is capable of performing synchronous read operations, an acknowledge signal is required to indicate that the synchronous read data is ready. The acknowledge signal undesirably requires an additional PCB routing wire.
It would therefore be desirable to have a memory system that can perform fully synchronous write and read operations, while multiplexing address and data signals on the same set of bus lines, and minimizing the required number of PCB routing wires. It would be desirable for the timing specifications of this memory system to be well defined with respect to a system clock signal, such that an acknowledge signal is not required to perform synchronous read operations. It would further be desirable for write address and write data signals to be processed in response to well defined clock edges, and for read data signals to be provided in response to well defined clock edges. It would further be desirable for the memory system to be capable of performing single address write/read operations, burst write/read operations, and repeat write/read operations in the A/D muxed mode.